specifcations subject to change without notice. all dimensions in inches. ? copyright 2011 the connor-winfeld corporation 2111 comprehensive drive aurora, illinois 60505 phone: 630- 851- 4722 fax: 630- 851- 5040 www.conwin.com 2111 comprehensive drive aurora, illinois 60505 phone: 630- 851- 4722 fax: 630- 851- 5040 www.conwin.com 5x7mm precision tcxo in stock at digi-key description: the connor-winfelds D75AS is a 5x7mm surface mount temperature compensated crystal controlled oscillator (tcxo) with a tri-state clipped sinewave output. through the use of analog temperature compensation, the D75AS is capable of holding sub 1-ppm stabilities over the 0 to 70c temperature range. operating specifcations parameter minimum nominal maximum units notes nominal frequency (fo) - 20.0 - mhz frequency calibration @ 25 c -1.0 - 1.0 ppm 1 frequency stability vs. temperature -0.25 - 0.25 ppm 2 frequency vs. load stability -0.25 - 0.25 ppm 5% frequency vs. voltage stability -0.25 - 0.25 ppm 5% static temperature hysteresis - - 0.4 ppm 3 freq, shift after refow soldering -1.0 - 1.0 ppm 4 aging (1st year) -1.0 - 1.0 ppm total frequency tolerance -4.6 - 4.6 ppm 5 operating temperature range: 0 - 70 c supply voltage (vcc) 3.135 3.3 3.465 vdc 5% supply current (icc) - - 6 ma period jitter - 3 5 ps rms integrated phase jitter - 0.5 1.0 ps rms 6 ssb phase noise at 10hz offset - -80 - dbc/hz ssb phase noise at 100hz offset - -110 - dbc/hz ssb phase noise at 1khz offset - -135 - dbc/hz ssb phase noise at 10khz offset - -150 - dbc/hz ssb phase noise at 100khz offset - -150 - dbc/hz start-up time - - 5 ms absolute maximum ratings parameter minimum nominal maximum units notes storage temperature -55 - 85 c supply voltage (vcc) -0.5 - 6.0 vdc input voltage -0.5 - vcc+0.5 vdc features: model: D75AS 3.3 vdc operation clipped sinewave output frequency stability: 0.25 ppm temperature range: 0 to 70c low jitter <1ps rms tri-state enable/disable function 5x7mm surface mount package tape and reel packaging rohs compliant / pb free us headquarters: 630-851-4722 european headquarters: +353-61-472221 package characteristics package hermetically sealed crystal mounted on a ceramic package notes: 1. initial calibration @ 25c. specifcations at time of shipment after 48 hours of operation. 2. frequency stability vs. change in temperature. [(fmax - fmin)/2.fo]. 3. frequency change after reciprocal temperature ramped over the operating range. frequency measured before and after at 25c 4. within two hours after refow 5. inclusive of calibration @ 25?c, frequency vs. change in temperature, change in supply voltage (5%), load change (5%), refow soldering process and 20 years aging, referenced to fo. 6. bw = 12 khz to 20 mhz. 7. leave pad 8 unconnected if enable / disable function is not required. when tri-stated, the output stage is disabled but the oscillator and compensation cir cuit are still active (current consumption < 1 ma). 8. output is ac coupled. 9. for best performance it is recommended that the circuit connected to this output should have an equivalent input capacitance of 10pf. environmental characteristics vibration: vibration per mil std 883e method 2007.3 test condition a shock: mechanical shock per mil std 883e method 2002.4 test condition b. soldering process; rohs compliant lead free. see soldering profle on page 2. ordering information d57as-025.0m* * for the tape and reel option, add -t to the end of the part number. example: D75AS-25.0m-t enable / disable input characteristics (pad 8) parameter minimum nominal maximum units notes enable voltage (high) 70%vcc - vdc 7 disable voltage (low) - - 30%vcc vdc 7 D75AS 1 144 20. 0 mhz bulletin tx243 page 1 of 2 revision 02 date 03 nov 2011 clipped sinewave output characteristics parameter minimum nominal maximum units notes voltage 1.0 - - v pk to pk 8 load resistance - 10k - ohm load - 10 - pf 9
specifcations subject to change without notice. all dimensions in inches. ? copyright 2011 the connor-winfeld corporation 2111 comprehensive drive aurora, illinois 60505 phone: 630- 851- 4722 fax: 630- 851- 5040 www.conwin.com suggested pad layout design recommendations output waveform tape and reel dimensions 1: do not connect 2: do not connect 3: do not connect 4: ground 5: output 6: do not connect 7: do not connect 8: tri-state enable / disable 9: supply voltage vcc 10: n/c pad connections solder profle 120c 150c 180c 260c 0 220c up to 120 s t ypical 10 s 60 to 90 s t ypical te mperature 260c meets ipc/jedec j-std-020c 120c 150c 180c 260c 0 220c up to 120 s t ypical 10 s 60 to 90 s t ypical te mperature 260c meets ipc/jedec j-std-020c package layout 200 mv/div 0 0.276 0.006 (7.0mm) 0.197 0.006 (5.0mm) 0.079 max. (2.0mm) D75AS 1 144 20.0 mhz 0.025( 6 places) (0.635mm) 0.100 (2.54mm) 0.040 (1.02mm) (6 places) 0.030 (0.762mm) (4 places) 0.100 (2.54mm) pi n 1 0.038 (0.965mm) (4 places) dimensional to lerance: .005 (.127mm) .02 (.508mm) 1 2 3 4 5 6 7 8 9 10 bottom vi ew meets eia-481a and eiaj-1009b 2,000 pcs/reel 8.46 di a (216mm dia) .08 (2.0mm) 1.00 di a (25mm dia) 9.84 di a (250mm dia) .06 di a (1.5mm dia) .69 (17.5mm) .08 (2.0mm) 3.15 (80mm) .315 (8.0mm) .08 (2.0mm) .21 (5.4mm) .157 (4.0mm) .31 (7.9mm) .295 (7.5mm) .07 (1.75mm) .83 (16.0mm) pin 1 direction of f eed (customer ) 0.215 (5.46mm) 0.037 (0.94mm) 0.051 (1.28mm) 0.051 (1.28mm) 0.295 (7.49mm) 0.030 (0.76mm) keep out area to p v iew 1 10 9 5 4 8 2 3 6 7 * do not route any traces in the keep out area. it is recommended the next layer under the keep out area is to be ground plane. 4 5 1 2 3 6 7 8 9 10 vcc supply v oltage n/c dnc dnc dnc dnc dnc 10 nf bypass enable/ disable output 10 pf ground 0.1 uf bypass dn c = do not connect 10k ohm osc to p l a yer ground la yer bo tt om la yer output buf fe r 50 oh m t r ace w ithout v ias ....... vcc , should have a l arge copper area fo r reduced inductance . connect a 0 .01uf bypass capacito r <0.1(2.54mm) fro m the pad . ground , should have a l arge copper area fo r reduced inductance . 0.010(0.254mm) r ecommended clearance inductance fo r internal copper flood . to p view 1 3 4 5 6 8 9 10 buffer ground 50 ohm trace <1by design vcc ground to p view test circuit ppurpiordodtnfiududolpimtodr uecurnvdxpt:ioipvdtrtdirdxomudntxuxdpodmuupdpfudxlunimntpiordxptputdordpfixdttptd xfuupdipdixd ueci utdpftpdpfudni ncipdnorrunputdpodpfixdadocplcpdmcxpdftdudpfuduecidtourpdirlcpdntltniptrnud pftpdixdxlunimutd:vdpfudromirtodoottdntltniptrnusduditpiorxdr omdpfudromirtodoottdntltniptrnudioodftdudtd i ttctputdurrunpdordpfudxpt:ioipvdordtll o8imtpuovdgdll:dlu dlhdoottdtirru urnus bulletin hgw.a page wapdaw revision mw date maaup?awmll
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